This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 11-071608, filed Mar. 17, 1999, the entire contents of which are incorporated herein by reference.
The present invention relates to a mirror circuit in which currents flow in constant-current transistors, respectively, each constant current being proportional to the gate width of the transistor. More particularly, the invention relates to a mirror circuit for use in an analog circuit incorporating a plurality of transistors, each receiving a constant current and generating a constant current, or in a high-speed IF (Interface) circuit designed for small signals.
Mirror circuits are known as circuits in which constant currents flow in constant-current transistors, respectively, each constant current being proportional to the ratio of the gate width to the gate length (dimension ratio) of the transistor.
FIG. 1 shows such a conventional mirror circuit. The mirror circuit comprises a constant-voltage generating circuit 101 and a plurality of N-channel MOS transistors (constant-current transistors), e.g., three N-channel MOS transistors Tr.1, Tr.2 and Tr.3. The constant-voltage generating circuit 101 comprises N-channel MOS transistor Tr.0. The circuit 101 receives a constant current I0 from a constant current circuit 102 (or an external terminal, not shown) and generates a constant bias voltage (constant voltage Vref). The constant-current transistors Tr.1, Tr.2 and Tr.3 receive the output (i.e., constant voltage Vref) of the constant-voltage generating circuit 101. In each of the transistors Tr.1, Tr.2 and Tr.3, there flows a constant current that is proportional to the ratio of the gate width to the gate length (hereinafter referred to as xe2x80x9cgate-width ratioxe2x80x9d). The transistors Tr.0, Tr.1, Tr.2 and Tr.3 have different gate widths W0, W1, W2 and W3, respectively, and have the same gate length L0. Hence, constant current W1/W0xc3x97I0 flows in the constant-current transistor Tr.1, constant current W2/W0xc3x97I0 flows in the constant-current transistor Tr.2, and constant current W3/W0xc3x97I0 flows in the constant-current transistor Tr.3.
In the mirror circuit described above, it is necessary to orientate the transistors Tr.1, Tr.2 and Tr.3 in the same direction as shown in FIG. 2, so that a constant current proportional to the gate-width ratio may flow in each constant-current transistor. In other words, the source (S)-drain (D) paths of transistors Tr.0, Tr.1, Tr.2 and Tr.3 must be orientated in the same direction. If the source (S)-drain (D) paths of transistors Tr.0, Tr.1, Tr.2 and Tr.3 are orientated in different directions as is illustrated in FIG. 3, the matching of the transistors Tr.0, Tr.1, Tr.2 and Tr.3 will deteriorate. The deterioration of the matching (so-called xe2x80x9cmatching failurexe2x80x9d) results from the difference between the transistors Tr.0, Tr.1, Tr.2 and Tr.3 in terms of threshold value (Vth) or current value (constant current I0). This difference has been caused by the erroneous orientation of the wafer or the slantwise implantation of ions in the process of manufacturing the mirror circuit. Consequently, a constant current proportional to the gate-width ratio cannot flow in each of the constant-current transistors Tr.1, Tr.2 and Tr.3. Thus, the matching failure deteriorates the circuit characteristics or the circuit margin.
To prevent the deterioration of the circuit characteristics or the circuit margin, the conventional mirror circuits are designed to orientate the constant-current transistors in the same direction, as much as is possible. Here arises a problem. The trend in recent years is to incorporate a mirror circuit into high-speed IF circuits designed for small signals. In a high-speed IF circuit for small signals, it is difficult, in some cases, to orientate all constant-current transistors Tr.1, Tr.2 and Tr.3 in the same direction in the I/O area 202 excluding the core area 201, as can be understood from FIG. 4.
As indicated above, a matching failure occurs if the constant-current transistors are orientated in different directions. A matching failure may also take place if the constant-current transistors are laid out, each remote from any other.
The object of the present invention is to provide a mirror circuit in which a transistor-matching failure can be prevented no matter how the transistors are laid out, thus inhibiting deterioration of the circuit characteristics and the circuit margin.
To achieve the object, a mirror circuit according to the invention comprises: a plurality of constant-current transistors; and a plurality of constant-voltage transistors. The constant-current transistors are provided removed from one another, for generating constant currents. Each of the constant-voltage transistors is provided an associated constant-current transistor located at a position, for generating a constant voltage to be applied to a gate of the associated constant-current transistor to make a source-drain current flow in the associated constant-current transistor. The source-drain current is proportional to a gate width of the associated constant-current transistor.
Another type of a mirror circuit according to the invention comprises: a plurality of constant-current transistors for generating constant currents; and a plurality of constant-voltage transistors. The constant-current transistors have source-drain paths orientated in different directions. Each constant-voltage transistor is provided for an associated constant-current transistor orientated in a direction, for generating a constant voltage to be applied to a gate of the associated constant-current transistor to make a source-drain current flow in the associated constant-current transistor. The source-drain current is proportional to a gate width of the associated constant-current transistor.
In the mirror circuits according to the invention, a constant voltage can be applied to each constant-current transistor in accordance with the direction in which the transistor is laid out or the position where the transistor is located. Thus, a source-drain current proportional to the gate width of the constant-current transistor flows in the constant-current transistor, even if it is difficult to lay out all constant-current transistors in the same direction or to arrange them close to one another. It is therefore possible to reduce the difference between the constant-current transistors in terms of threshold value and current value, which results from the different layout directions and positions of the constant-current transistors.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.